FIG. 1 shows a prior art static random access memory (SRAM) cell 10. Memory cell 10 comprises n-channel pull-down (drive) transistors 12 and 14 having drains respectively connected to pull-up load elements or resistors 16 and 18. Transistors 12 and 14 are typically metal oxide silicon field effect transistors (MOSFETs) formed proximate an underlying silicon semiconductor substrate.
The source regions of transistors 12 and 14 are tied to a low reference or circuit supply voltage, labeled V.sub.SS and typically referred to as "ground." Resistors 16 and 18 are respectively connected in series between a high reference or circuit supply voltage, labeled V.sub.CC, and the drains of transistors 12 and 14, respectively. The drain of transistor 14 is connected to the gate of transistor 12 by a line 20, and the drain of transistor 12 is connected to the gate of transistor 14 by a line 22 to form a flip-flop having a pair of complementary two-state outputs.
A memory flip-flop, such as that described above in connection with FIG. 1, typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 24 and 26, are used to selectively address and access individual memory elements within the array. Access transistor 24 has one active terminal connected to the drain of transistor 12. Access transistor 26 has one active terminal connected to the drain of transistor 14. A plurality of complementary column line pairs, such as the single shown pair of complementary column lines 28 and 30, are connected to the remaining active terminals of access transistors 24 and 26. A row line 32 is connected to the gates of access transistors 24 and 26.
Reading static memory cell 10 involves activating row line 32 to connect outputs 34 and 36 to column lines 28 and 30. Writing to static memory cell 10 involves first placing selected complementary logic voltages on column lines 28 and 30, and then activating row line 32 to connect those logic voltages to outputs 34 and 36. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
A static memory cell is said to be bi-stable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The two possible output voltages produced by a static memory cell correspond generally to upper and lower circuit supply voltages. Intermediate output voltages, between the upper and lower circuit supply voltages, generally do not occur except during brief periods of memory cell power-up and during transitions from one operating state to the other operating state.
FIG. 2 illustrates a fragmentary cross-sectional view of a prior art layout of portions of the FIG. 1 SRAM schematic pertinent to this disclosure. Referring to FIG. 2, a semiconductor wafer substrate 40 is illustrated. Pull-down transistor device 12 and access device transistor 24 are formed proximate substrate 40. Transistor devices 12 and 24 comprise gates 42 and 44, respectively. Sidewall spacers 46 are formed adjacent gates 42 and 44. Transistor device 12 comprises a source 50 and a drain 52. Source 50 is in electrical connection with V.sub.SS and drain 52 is in electrical connection with resistor 16. Further, drain 52 comprises a common diffusion region which is also a source for access transistor device 24. Access device 24 further comprises a drain 54 which is in electrical connection with column line 28. Transistor devices 12 and 24 are commonly n-type MOSFETs (i.e., NMOS transistors). Accordingly, semiconductor substrate 40 generally comprises a background p-type doping. A typical background dopant concentration is from about 10.sup.15 to about 10.sup.18 atoms/cm.sup.3. Source/drain regions 50, 52 and 54 are formed of n-type conductivity-enhancing dopant provided to a concentration which overwhelms the background p-type doping. A typical source/drain dopant concentration is from about 10.sup.19 to about 10.sup.21 atoms/cm.sup.3.
Also shown in FIG. 2 is an n-type collector region 60 formed beneath devices 12 and 24. N-type collector region is preferably kept at a potential of about 3.3 volts and functions to collect spurious electrons generated by, for example, alpha particle hits into substrate 40. N-type collector region 60 typically comprises an n-type dopant concentration of about 10.sup.17 atoms/cm.sup.3 which is implanted to a depth of from about 1 to about 4 microns beneath an upper surface of wafer substrate 40.
Alpha particles are naturally occurring ionizing radiation which can penetrate into a silicon substrate and generate electron-hole pairs. One source of alpha particles is the decay of radioactive impurities such as uranium or thorium, known to be present in trace levels in common semiconductor packaging materials. The alpha particles can generate sufficient charge adjacent an SRAM memory cell node to upset the data state of the SRAM memory cell. Such events are termed "soft errors." Soft error rates must be controlled to very low levels for reliable operation of semiconductor devices. The shown n-type collector region 60 is a prior art method of reducing soft error rate. Specifically, electrons generated by alpha particles are attracted to collector region 60 and trapped therein. However, a difficulty can occur if the electrons are generated closer to source/drain region 52 than to collector region 60 in that the electrons will frequently be attracted preferentially to source/drain region 52 and thereby potentially cause a soft error rate in an SRAM memory cell device.
It would be desirable to develop alternative methods of protecting SRAM devices and integrated circuitry from alpha particle hits. Preferably, such alternative methods would better protect a drain region of a pull-down transistor, or a source region of an access device transistor, than does the n-type collector region discussed above in describing the prior art. Also, it would be desirable to develop methods for protecting devices from alpha particle inflicted damage which do not require n-type collector regions. Such methods would advantageously eliminate the processing steps required to form n-type collector regions.